1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus and image pickup system and, more particularly, to a solid-state image pickup apparatus having a pixel including a photoelectric conversion unit, a read transistor for reading a signal from the photoelectric conversion unit, and a reset transistor for supplying a reset signal to the input portion to reset the input portion of the read transistor, and an image pickup system using such the apparatus.
2. Related Background Art
Conventionally, a CCD has been often used as a solid-state image pickup apparatus because of its high S/N ratio. On the other hand, a so-called amplification type solid-state image pickup apparatus that is advantageous in a simple manner of use or low power consumption has also been developed. An amplification type solid-state image pickup apparatus supplies signal charges accumulated in a light-receiving pixel to the control electrode of a transistor in the pixel unit and outputs an amplified signal from the main electrode. Examples of amplification type solid-state image pickup apparatus transistors are a SIT image sensor using a SIT (static induction transistor) as an amplification transistor, a BASIS using a bipolar transistor, a CMD using a JFET (junction field effect transistor) whose control electrode is depleted, and a CMOS sensor using a MOS transistor. Especially, extensive efforts have been made to develop a CMOS sensor because it satisfactorily matches with a CMOS process and can form a peripheral CMOS circuit on one chip.
FIG. 4 is a circuit diagram showing a conventional CMOS image sensor. The FIG. 4 illustrates 2×2 pixels for simplification. The sensor includes a unit pixel 1, a photodiode 2 for receiving light and accumulating signal charges, a signal charge amplification MOS transistor 3, a transfer MOS transistor 4 for transferring the signal charges accumulated in the photodiode 2 to the gate electrode unit of the MOS transistor 3, a reset MOS transistor 5 for resetting the gate electrode potential of the MOS transistor 3, and a power supply potential supply line 6 to which the drain electrode of the reset MOS transistor 5 and that of the amplification MOS transistor 3 are commonly connected. The sensor also has a selection switch MOS transistor 7 for selecting an output pixel, and a pixel output line 8. When the selection switch MOS transistor 7 is turned on, the source electrode of the amplification MOS transistor 3 is electrically connected to the output line 8, and the signal output from a selected pixel is supplied to the output line 8. A constant current supply MOS transistor 9 supplies the amplification MOS transistor 3 with a load current through the pixel output line 8 and the selection switch MOS transistor 7 of a selected pixel to make the amplification MOS transistor 3 with operate as a source follower and to output a potential having a predetermined voltage difference from the gate potential of the MOS transistor 3 to the output line 8.
A transfer control line 10 controls the gate potential of the transfer MOS transistor 4. A reset control line 11 controls the gate potential of the reset MOS transistor 5. A selection control line 12 controls the gate potential of the selection MOS transistor 7. A constant potential supply line 13 supplies a predetermined potential to the gate of the MOS transistor 9 such that the MOS transistor 9 performs a saturation region operation and serves as a constant current source. A pulse terminal 14 supplies a transfer pulse to the transfer control line 10. A pulse terminal 15 supplies a reset pulse to the reset control line 11. A pulse terminal 16 supplies a selection pulse to the selection control line 12. A vertical scanning circuit 17 sequentially selects the rows of pixels arrayed in a matrix. Output lines 18 of the vertical scanning circuit 17 comprise a first row
selection output line 18-1 and a second row selection output line 18-2. A switch MOS transistor 19 supplies a pulse from the pulse terminal 14 to the transfer control line 10. A switch MOS transistor 20 supplies a pulse from the pulse terminal 15 to the reset control line 11. A switch MOS transistor 21 supplies a pulse from the pulse terminal 16 to the selection control line 12. The gates of the MOS transistors 19, 20, and 21 are connected to the row selection output line 18-1. The state of the row selection output lines 18-1 and 18-2, determines the row on which pixels become active.
The sensor also includes an readout circuit 22 for reading out an output from a pixel, a capacitor 23 for holding a reset signal output from a pixel, a capacitor 24 for holding a photo signal output from a pixel, a switch MOS transistor 25 for connecting/disconnecting the pixel output line 8 to/from the capacitor 24, a noise output line 27 to which the reset output held by the capacitor 23 is supplied, a signal output line 28 to which the optical output held by the capacitor 24 is supplied, a switch MOS transistor 29 for connecting/disconnecting the capacitor 23 to/from the noise output line 27, a switch MOS transistor 30 for connecting/disconnecting the capacitor 24 to/from the signal output line 28, a noise output line reset MOS transistor 31 for resetting the potential of the noise output line 27, a signal output line reset MOS transistor 32 for resetting the potential of the signal output line 28, a power supply terminal 33 for supplying a reset potential to the source electrodes of the reset MOS transistors 31 and 32, a horizontal scanning circuit 34 for sequentially selecting the capacitors 23 and 24 which are arranged for each column of pixels arrayed in a matrix, an output line 35-1 for selecting the first column, and an output line 35-2 for selecting the second column. The output lines of the horizontal scanning circuit 34 are connected to the switch MOS transistors 29 and 30. A pulse supply terminal 36 applies a pulse to the gates of the reset MOS transistors 31 and 32. Pulse supply terminals 37 and 38 apply pulses to the gates of the switch MOS transistors 25 and 26, respectively. A differential amplifier 39 amplifies and outputs the voltage difference between the potential of the noise output line 27 and that of the signal output line 28. The differential amplifier 39 has an output terminal 40.
The operation of the sensor shown in FIG. 4 will be described next with reference to the timing chart shown in FIG. 5. Note that all MOS transistors shown in FIG. 4 are NMOS transistors which are turned on when the gate potential is at high level and off at low level. Numorals indicating timing pulses in FIG. 5 correspond to the reference numerals of pulse input terminals in FIG. 4.
When the row selection output line 18-1 goes high upon operation of the vertical scanning circuit 17, operation of the first row of the pixel matrix is enabled. When the pulse terminal 16 goes high, the source of the amplification MOS transistor 3 of each pixel is connected to the constant current supply 9 through the output line 8, so the source follower output of the pixel is output to the output line 8. When the pulse terminal 15 goes high, the gate portion of the amplification MOS transistor 3 is reset by the reset MOS transistor 5. When a High pulse is applied to the pulse supply terminal 37 next, the reset output of the pixel is accumulated in the capacitor 23 through the MOS transistor 25.
When a High pulse is applied to the terminal 14, signal charges accumulated in the photodiode 2 are transferred to the gate of the MOS transistor 3 through the transfer MOS transistor 4. Subsequently, when a High pulse is applied to the terminal 38, an output in which a signal is superposed on the reset output of the pixel is accumulated in the capacitor 24 through the MOS transistor 26. Th reset output of the pixel varies because the threshold voltage of the MOS transistor 3 varies among the pixels. Hence, the difference between the outputs accumulated in the capacitors 23 and 24 is a pure signal free from noise. When the horizontal scanning circuit 34 is operated, the output lines 35-1 and 35-2 sequentially go high, and the outputs accumulated in the capacitors 23 and 24 of each column are supplied to the horizontal output lines 27 and 28 through the MOS transistors 29 and 30, respectively. Before the High pulses from the output lines 35-1 and 35-2 are output, the terminal 36 is set at high level to reset the horizontal output lines 27 and 28 through the MOS transistors 31 and 32 in advance. The pixel reset output and the signal output superposed on the pixel reset level, which are supplied to the horizontal output lines 27 and 28, are input to the differential amplifier 39. A pixel signal obtained by subtracting the reset level, i.e., a pixel signal free from noise is output from the output terminal 40.
In the prior art, however, since the number of MOS transistors of one pixel and the number of control lines are large, a small pixel in size is hard to realize. That is, in the prior art shown in FIG. 4, one pixel has four MOS transistors and three control lines in addition to a photodiode, power supply line, and pixel output line. Unlike a pixel of a CCD with a simple arrangement, size reduction is hard for CMOS sensors.